Computer designers are always searching for faster memory devices that will allow them to design faster computers. A significant limitation on a computer's operating speed is the time required to transfer data between a processor and a memory circuit, such as a read or write data transfer. Memory circuits, such as a dynamic random access memories (DRAMs), usually include a large number of memory cells arranged in one or more arrays, each having rows and columns. The memory cells provide locations at which the processor can store and retrieve data. The more quickly the processor can access the data within the memory cells, the more quickly it can perform a calculation or execute a program using the data.
FIG. 1 shows, in part, a typical computer architecture. A central processing unit (CPU) or processor 50 is connected to a bus 52, which in turn is connected to a system or memory controller 54 and a datapath integrated circuit (IC) 56. The memory controller 54 and the datapath IC 56 serve as interface circuitry between the processor 50 and a memory device 60. The processor issues a command C and an address A which are received and translated by the memory controller 54, which in turn applies command signals and an address to the memory device 60. Corresponding to the processor-issued commands C and addresses A, data D is transferred between the processor 50 and the memory device 60 via the datapath IC 56.
Illustrative of the type of memory devices 60 currently used, is a synchronous dynamic random access memory (SDRAM) device 100 shown as a block diagram in FIG. 2. The memory device 100 includes as its central memory element two memory array banks 101A and 101B, which operate under the control of a control logic circuit 102. Each of the memory arrays 101A & B includes a plurality of memory cells (not shown) arranged in rows and columns. For purposes of discussion, the memory device 100 has an 8-bit word width--meaning that to each specified memory address (combined bank, row and column address) there is a one-to-one correspondence with 8 memory cells in one of the arrays 101A & B, and the processor 50 (see FIG. 1) operates on data elements of 8 bits each.
A system clock (not shown) provides a signal CLK to the control circuit 102 of the memory device 100, as well as to the processor 50 and controller 54 (see FIG. 1) accessing the memory device. Command signals input to the control circuit 102 are decoded by command decode circuitry 104. These signals are well known in the art, and include signals such as RAS (row address strobe), CAS (column address strobe) and WE (write enable). Distinct combinations of the various command signals constitute distinct commands. For example, the combination of RAS low, CAS high and WE low can represent a PRECHARGE command. Examples of other well known commands include ACTIVE, READ, WRITE and NOP. Corresponding to the applied command, the control circuit 102 sends control signals on control lines 103A-H to other parts of the memory device 100, controlling the timing of access to the memory cells in arrays 101A and 101B.
An address is input to an address register 106, indicating the memory location to be accessed. The address specifies one of the memory banks 101A & B and a row and column address within the specified bank. The address register 106 provides the address information to the control circuit 102, and to a row-address mux 107 and a column-address latch and decode circuit 110. The row-address mux 107 multiplexes the row address information and provides it to one of row-address latch and decode circuits 108A and 108B corresponding to the one of the memory banks 101 A & B to be accessed. Each of the row latch and decode circuits 108A and 108B takes a row address provided by the row-address latch 107 and activates a selected row of memory cells (not shown) in the memory array 101A and 101B by selecting one of several row access lines 112A and 112B, all respectively. The column latch and decode circuit 110 takes a column address provided by the address register 106 and selects one of several column access lines 114A and 114B, each of which is coupled to one of the memory arrays 101A and 101B by one of I/O interface circuits 116A and 116B, all respectively. Each of the I/O interface circuits 116A & B selects the memory cell(s) corresponding to the column location in an activated row. The I/O interface circuits 116 include sense amplifiers which determine and amplify the logic state of the selected memory cells, and I/O gating of data to and from a data I/O register 118. The data register 118 is connected to a data bus which is used to input and output data to and from the memory device 100.
Data transfer cycles typically involve several steps and each step takes time. For example, a read access requires the control logic circuit 102 of the memory device 100 to decode commands and the memory cell address; and to provide control signals to the circuitry accessing the memory array banks 101A and 101B in order to activate the selected row in the selected memory bank, allow time for sense amplifiers to develop signals from the selected column in the memory bank, transfer data from these sense amplifiers to the data register 118 where the data is then made available on the data bus, and terminate the cycle by precharging the row for subsequent access. Steps that are particularly time consuming include the activation step, the read latency (the time between registration in the memory device of a read command and the availability of the accessed data on the data bus), and the precharge step.
In applications involving a continuous flow of data such as Graphics, Video and Communications, a page-oriented memory device is desirable because it can reduce the number of activation and precharge steps performed. When a memory device is operated in a page mode cycle, a row is activated, and data transfers occur, at a large number (sometimes all) of the columns in that row before completion of the cycle with a row precharge step. This contrasts with the conventional data transfer cycle where a single column is accessed in the activated row, the row is then precharged, and the next data transfer cycle is initiated with a new set of activation and precharge steps.
When access is sought to a row other than one currently open in the page-oriented memory device (sometimes referred to as a "page miss" in the art), a new page mode cycle is initiated, complete with activation and precharge steps. Thus, a page-oriented memory device allows a continuous flow of data to and from one row, but interrupts that data flow during the time required to shut down the one row and access the other row.
One way of partly eliminating the interrupted data flow associated with a page miss is to define multiple memory cell array banks, as shown in the memory device 100 of FIG. 2. For example, when a series of accesses to Row I (not shown) in Bank 101A is performed and subsequent access to Row J (not shown) in Bank 101B is required, the activation step can be initiated in Bank 101B while access is continuing in Bank 101A. If initiation of access to Row J in Bank 101B occurs early enough, the time delay associated with the precharge of Row I in Bank 101A, activation of Row J in Bank 101B, and read latency (if applicable) can be hidden--meaning that there is no interruption in the flow of data due to the change of rows.
The currently used multiple bank approach is, however, of no benefit if the Row I currently being accessed and the Row J subsequently to be accessed are in the same one of Banks 101 A & B. In this case the data bus is idle for the entire precharge time of Row I and the activation time and read latency (if applicable) of Row J. FIGS. 3-6 illustrate this disruption of the data flow associated with a page miss.
Each of FIGS. 3-6 shows the clock signal CLK with leading edges occurring at T0, T1, T2, etc.; the commands supplied to the memory device 100 and registered therein at times corresponding to leading edges of the clock signal; and the state of the data bus on which data is output (DOUT) from or input (DIN) to the memory device at a time corresponding to a leading edge of the clock signal. The FIGS. 3-6 are representative of the current state of the art: corresponding to a selected clock speed of 100 MHz, the precharge time .sup.t RP is of duration 3 clock cycles (i.e., 30 ns), the activation time .sup.t RCD is 3 clock cycles, the read latency is 3 clock cycles, and the write recovery time .sup.t WR (the time between registration in the memory device of input data DIN and the availability of the write-accessed row for the row-deactivating precharge step) is 2 clock cycles.
FIG. 3 shows a read access to one row being terminated by registration and execution in the memory device 100 of a PRECHARGE command, and the subsequent activation of another row by an ACTIVE command, followed by a READ command. The data bus is idle for 7 clock cycles between the last availability of data DOUT from the one row and the first availability of data DOUT from the other row. FIG. 4 shows a read access to one row being terminated by a PRECHARGE command, and the subsequent activation of another row by an ACTIVE command, followed by a WRITE command. The data bus is idle for 4 clock cycles between the last availability of data DOUT from the one row and the first availability of data DIN for the other row. Most dramatic is the transition from a write access in one row followed by a read access in another row, as shown in FIG. 5. In this case, the data bus is idle for 10 full clock cycles. FIG. 6 shows the data bus idling for 7 clock cycles during a transition from a write access in one row to a write access in another row.
In addition to not completely solving the problem of excessive data bus idle time for successive page miss accesses, the currently used multiple bank approach has a number of drawbacks. The memory controller 54 (see FIG. 1) is made more complicated, because it must keep track of which rows are open in what banks. Alternatively, the memory controller 54 could always close a row after accessing it, but this then eliminates the possibility of a "page hit" if subsequent access is to that same row. Additionally, a means for independently addressing the multiple banks and providing independent commands to multiple banks at appropriate times further complicates the control circuit 102 and other circuitry internal to the memory device 100 (see FIG. 2).